The proliferation and increased usage of portable computer and electronic devices has greatly increased demand for memory cells. Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity memory cells (e.g., flash memory, smart media, compact flash, or the like). Memory cells can generally be subdivided into volatile and non-volatile types. Volatile memory cells usually lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory cells include, for example, random access memory (RAM), DRAM, SRAM and the like. Non-volatile memory cells maintain their information whether or not power is maintained to the devices. Non-volatile memory cells include, but are not limited to, ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash EEPROM the like. Volatile memory cells generally provide faster operation at a lower cost as compared to non-volatile memory cells.
Memory cells often include arrays of memory cells. Each memory cell can be accessed or “read”, “written”, and “erased” with information. The memory cells maintain information in an “off” or an “on” state, also referred to as “0” and “1”. Typically, a memory cell is addressed to retrieve a specified number of byte(s) (e.g., 8 memory cells per byte). For volatile memory cells, the memory cells must be periodically “refreshed” in order to maintain their state. Such memory cells are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states.
At the same time, the increased demand for information storage is commensurate with memory cells having an ever increasing storage capacity (e.g., increase storage per die or chip) and the progress of integrated circuit technology has been marked by a continuing reduction in the size of memory cells. Smaller devices yield the dual advantages of greater packing density and increased speed. Nonetheless, defining smaller as well as denser features, is limited to the lithographic resolution processes employed in creating these features.
Features have been conventionally defined by an inlay process wherein, the substrate surface, including memory cells and other devices formed on the wafer, is first covered with a dielectric layer such as oxide. A patterned photoresist profile is then formed on the dielectric surface. The resist profile has openings, or holes, in the photoresist corresponding to the areas where vias are to be formed in the dielectric. Other areas of the resist are formed into elongated openings to create interconnect lines. The photoresist-covered dielectric layer is then etched to remove oxide underlying the openings in the photoresist. The photoresist is then stripped away. Copper or another suitable metal is then used to fill the vias and interconnects, the metal typically being deposited by chemical vapor deposition (CVD). The result is a dielectric layer with conductive metal at various levels therein. The surface of the dielectric layer is typically smoothed using a CMP process. Additional dielectric layers are then added to complete the required interconnections for the chip. Such dielectric layers with interconnects and vias formed by the inlay processes are sometimes referred to as interlevel dielectrics or, alternatively, as inter level dielectric layers.
Initially, visible light was used, but the desire for smaller feature size has led to the use of UV light and x-rays. Accordingly, by employing high-resolution photolithography, ultra-thin lines and vias are created in the dielectric. Patterns of openings are formed in the overlying photosensitive resist by directing the desired patterns of light onto the photoresist, the light being of a wavelength to which the photoresist is sensitive. Subsequently, the photoresist is “developed” to remove the light-exposed areas, leaving behind a photoresist mask on the surface of the dielectric. The photoresist mask is then used as a pattern in subsequent etching of the underlying dielectric. As such, the lithographic resolution affects, and the minimum feature size as well as the creation of the various features of the memory cells, is thus limited by the lithographic resolution. Accordingly, there exists a need for increasing the memory storage of semiconductor chips while employing the lithographic techniques for semiconductor fabrication.